Single crystal TFT from continuous transition metal delivery method

ABSTRACT

A TFT fabricated from a single crystal grain, and fabrication method has been provided. A large crystal grain is made by precise control of annealment, transition metal concentration, the density of transition metal nucleation sites, and the distance between nucleation sites. In one aspect of the invention, a diffusion layer permits the continual delivery of transition metal at a rate that both supports the lateral growth of di-silicide, and large distances between nucleation sites.

BACKGROUND AND SUMMARY OF THE INVENTION

[0001] This invention relates generally to thin-film transistor (TFT)processes and fabrication, and more particularly, to a TFTpolycrystalline film, and method of forming large grain sheets ofpolycrystalline silicon using transition metals semiconductor compounds,such as nickel silicide, to induce the crystallizing of an amorphousfilm through lateral growth from selective locations on a silicon wafer.

[0002] The demand for smaller electronic consumer products with higherresolution displays, spurs continued research and development in thearea of liquid crystal displays (LCDs). The size of LCDs can bedecreased by incorporating the large scale integration (LSI) and verylarge scale integration (VLSI) driver circuits, presently on theperiphery of LCDs, into the LCD itself. The elimination of externallylocated driving circuits and transistors will reduce product size,process complexity, a number of process steps, and ultimately the priceof the product in which the LCD is mounted.

[0003] The primary component of the LCD, and the component that must beenhanced for further LCD improvements to occur, is the thin-filmtransistor (TFT). TFTs are typically fabricated on a transparentsubstrate such as quartz, glass, or even plastic. TFTs are used asswitches to allow the various pixels of the LCD to be charged inresponse to the driver circuits. TFT performance will be improved, anddriver circuit functions incorporated into TFTs, by increasing theelectron mobility in the TFT devices. Increasing the electron mobilityof a transistor results in a transistor having faster switching speeds.Improved TFTs having increased electron mobility yield smaller LCDscreens, lower power consumption, and faster transistor response times.Further LCD resolution enhancements will require that the TFTs mountedon the transparent substrates have electron mobility characteristicsrivaling IC driver circuits currently mounted along the edges of thescreen. That is, display and driver TFT located across the entiredisplay must operate at substantially the same level of performance.

[0004] The carrier mobility of typical thin-film transistors, withactive areas formed from amorphous film, is poor, on the order of 0.1 to0.2 cm²/Vs. Carrier mobility is improved by using crystallized silicon.Single crystal silicon transistors, which are usually used in TFT drivercircuits, have electron mobilities on the order of 500 to 700 cm²/Vs.Polycrystalline silicon transistor performance is between the twoextremes, having mobilities on the order of 10 to 400 cm²/Vs. Thin-filmtransistors having mobilities greater than 100 cm²/Vs would probably beuseful in replacing LCD periphery mounted driver circuitry. However, ithas been difficult to produce polycrystalline TFTs with electronmobilities of even 40 to 50 cm²/Vs.

[0005] Single crystal silicon films, for use with LCDs, are difficult tofabricate when adhered to relatively fragile transparent substrates. Aquartz substrate is able to withstand high process temperatures, but itis expensive. Glass is inexpensive, but is easily deformed when exposedto temperatures above 600° C. for substantial lengths of time. Even thefabrication of polycrystalline silicon transistors has been verydifficult due to the necessity of using low temperature crystallineprocesses when glass is involved. Current polycrystallization processestypically require annealing times of approximately 24 hours, at 600° C.,to produce TFTs having a mobility of approximately 30-50 cm²/Vs. Theseprocesses are not especially cost effective due to the long processtimes, and the TFTs produced are not suitable for LCD driver circuits.

[0006] The process of heating amorphous silicon to form crystallizedsilicon is not entirely understood, and research on the subjectcontinues. Variations in temperature, film thickness, the degree towhich the amorphous matter melts, impurities in the film, and a range ofother factors influence the annealing of amorphous silicon. Generally,large grains of crystallization, or crystallization able to support highcarrier mobilities, occur in a polycrystalline film at a specifictemperature near the melting point. Temperatures below this preferredtemperature do not melt the amorphous silicon enough to form large grainareas, or to form uniformly crystallized film. Temperatures above thepreferred temperature rapidly lead to bulk nucleation. The bulknucleation of amorphous matter results in the spontaneouscrystallization of an amorphous film into relatively small grain sizesso that the electron mobility is relatively poor.

[0007] Various annealing methods exist for turning amorphous siliconinto polycrystalline silicon. The direct deposition of amorphous siliconfilm is probably the cheapest method of fabricating TFTs. Typically, thetransparent substrate is mounted on a heated susceptor. The transparentsubstrate is exposed to gases which include elements of silicon andhydrogen. The gases decompose to leave solid phased silicon on thesubstrate. In a plasma-enhanced chemical vapor deposition (PECVD)system, the decomposition of source gases is assisted with the use ofradio frequency (RF) energy. A low-pressure (LPCVD), or ultra-highvacuum (UHV-CVD), system pyrolytically decomposes the source gases atlow pressures. In a photo-CVD system the decomposition of source gasesis assisted with photon energy. In a high-density plasma CVD systemhigh-density plasma sources, such as inductively coupled plasma andhelicon sources, are used. In a hot wire CVD system the production ofactivated hydrogen atoms leads to the decomposition of the source gases.However, TFTs made from direct deposition have poor performancecharacteristics, with mobilities on the order of 1 to 10 cm²/Vs.

[0008] Solid phase crystallization (SPC) is a popular method ofcrystallizing silicon. In this process, amorphous silicon is exposed toheat approaching 600° C. for a period of at least several hours.Typically, large batches of LCD substrates are processed in a furnacehaving a resistive heater source. TFTs made from this crystallizationprocess are more expensive than those made from direct deposition, buthave mobilities on the order of 50 cm²/Vs. A rapid thermal anneal (RTA)uses a higher temperature, but for very short durations of time.Typically, the substrate is subjected to temperatures approaching 700 or800° C. during the RTA, however, the annealing process occurs relativelyquickly, in minutes or seconds. Glass substrates remain unharmed due tothe short exposure time. Because the process is so rapid, it iseconomical to process the substrates serially. Single substrates canalso be brought up to annealing temperatures faster than large batchesof substrates. A tungsten-halogen, or Xe Arc, heat lamp is often used asthe RTA heat source.

[0009] An excimer laser crystallization (ELC) process has also been usedwith some success in annealing amorphous silicon. The laser allows areasof the amorphous film to be exposed to very high temperatures for veryshort periods of time. Theoretically, this offers the possibility ofannealing the amorphous silicon at its optimum temperature withoutdegrading the transparent substrate upon which it is mounted. However,use of this method has been limited by the lack of control over some ofthe process steps. Typically, the aperture size of the laser isrelatively small. The aperture size, power of the laser, and thethickness of the film may require multiple laser passes, or shots, tofinally anneal the silicon. Since it is difficult to precisely controlthe laser, the multiple shots introduce non-uniformity's into theannealing process. Further, the wafers must be annealed serially,instead of in a furnace in batches. Although mobilities of over 100cm²/Vs are obtainable, TFTs made by this method are significantly moreexpensive than those made by direct deposition or SPC.

[0010] Also under investigation is the use of metal, such as aluminum,indium tin oxide, and transition metals such as nickel, cobalt, andpalladium to encourage the crystallization of silicon. Nickel seemsespecially promising, as the lattice mismatch between nickel di-silicideand silicon is small, less than 1%. In general, nickel has been used toreduce the annealing temperature typically required in a conventionalsolid phase crystallization (SPC) from approximately 600° C. to atemperature in the range between approximately 500 to 550° C., so thatthe LCD substrates are less susceptible to shrinkage. The use of nickelalso significantly shortens the annealing process times. TFTs madethrough this process are comparable in cost with those made by the SPCmethod, and the mobilities of metal-induced TFTs can approach 100cm²/Vs.

[0011] However, metal-induced crystallization requires the deposition ofa transition metal on an amorphous silicon film, and annealment of thetransition metal with the amorphous silicon. The result of annealing isdependent on how far the transition metal compounds have spread into theamorphous film. The possible results of annealment are unreactedamorphous silicon (or bulk nucleated silicon), unreacted transitionmetal, mono-silicide, and di-silicide. All of these compounds can inducehigh leakage currents in a transistor.

[0012] Liu et al., U.S. Pat. No. 5,147,826, disclose the deposition of anon-continuous metal film on amorphous silicon so that the annealingtemperature can be reduced to approximately 550 to 650° C. Fornash etal., U.S. Pat. No. 5,275,851 disclose a method of depositing extensiveareas of metal film to silicon, and low annealing temperatures tocrystallize silicon. However, neither method fosters thesilicide-enhanced lateral crystal growth needed to fabricatepolycrystalline silicon TFTs with very high electron mobility. Neithermethod discloses a method of controlling the lateral growth of silicideto eliminate unreacted metal and silicides in key areas of thetransistor.

[0013] A method of rapid thermal annealing nickel silicide withamorphous silicon is presented in co-pending U.S. patent Ser. No.08/879,386, filed Jun. 20, 1997, entitled “Thin-Film TransistorPolycrystalline Film Through Nickel Induced, Rapid Thermal Annealing andMethod for Same”, invented by Masashi Maekawa, Attorney Docket No. SMT258, which is assigned to the same assignees as the instant application.This patent application discloses the use of an RTA process to increasethe quality of the polycrystalline, and to reduce annealing times.However, the invention does not disclose a method of preventing theincursion of nickel into sensitive areas of a transistor.

[0014] A method of selectively depositing nickel silicide to crystallizetransistor source/drain regions in a two-step annealing process ispresented in co-pending U.S. patent Ser. No. 08/893,285, filed Jul. 15,1997, entitled “Selective Silicide Thin-Film Transistor and Method forSame”, invented by Masashi Maekawa, Attorney Docket No. SMT 239, whichis assigned to the same assignees as the instant application. However,metal-induced annealment processes, in the later stages of transistorfabrication, can be cumbersome in some applications.

[0015] A method of selectively locating nickel nucleation sites to formlarge crystal grains is presented in co-pending U.S. patent Ser. No.09/092,831, filed Jun. 5, 1998, entitled “Selected Site, Metal-Induced,Continuous Crystallization and Method for Same”, invented by Maekawa etal., which is assigned to the same assignees as the instant application.However, the above-mention invention cannot insure that the crystalgrains formed will be large enough to form a transistor.

[0016] It would be advantageous if metal-induced annealment processescould be used to fabricate broad areas of high quality polycrystallinefilms in critical areas of the transistor.

[0017] It would be advantageous if transistor active areas could beformed with a transition metal at an early stage of transistorfabrication.

[0018] It would be advantageous if the unreacted transition metals andsilicide products could be easily removed after annealment.

[0019] It would be advantageous if a TFT transistor could be formed froma single crystal grain to enhance performance.

[0020] Accordingly, a method for crystallizing an amorphous film intolarge grains comprising the steps of:

[0021] a) depositing a layer of the amorphous film;

[0022] b) implanting or depositing (alternatively referred to as doping)a first concentration of transition metal on the amorphous film, to forma first density of transition metal nucleus sites, with the nucleationsites being separated by a first distance, whereby a low density ofnucleation sites is formed; and

[0023] c) annealing to form large areas of single grain crystallizedfilm, whereby a crystallized film is prepared for the fabrication of ahigh electron mobility transistors.

[0024] An ion implantation method implants transition metal within arectangular window having a width in the range from 20 to 50 microns anda length of at least 50 microns. The exact length is dependent on thenumber of crystallization sites to be formed. In this manner, aconcentration of transition metal no more than 2×10¹⁹ atoms per cubedcentimeter, and a density of transition metal nucleus sites no more than1×10⁷ square centimeters is maintained. The distance between transitionmetal nucleus sites is no less than 2 microns.

[0025] A diffusion layer is used in a continual transition metaldelivery system aspect of the invention. Then, Step b) is performed, atleast partially, simultaneously with the performance of Step c). In thismanner, transition metal is continually introduced during the annealingprocess to support the lateral growth of crystallization, withoutincreasing the metal concentration above the defined minimum. Aninsulator film having a first thickness is deposited over the amorphousfilm. The transition metal is deposited over the insulator film andselectively etched to form a predetermined window size. Alternately, theinsulator film is selectively thinned to define a window with a firstthickness before the deposition of metal. Either way, Step c) includesthe diffusion of transition metal through the first thickness ofinsulator film into the amorphous film, whereby the density oftransition metal nucleuses is controlled.

[0026] When a single crystallized site is to be formed, the ratio of thetransition metal window to the first area of crystallized film is in therange from 1:1 to 1:3. When multiple single crystal sites are to beformed, the ratio is greater than 1:1. Step c) includes the first areaof crystallized film being in the range from 20 to 8,000 square microns(μ²), which is the area of a circle with a diameter in the range between5 and 100 microns.

[0027] A further steps, precedes Step c), of:

[0028] b₁) ramping the temperature up to the annealing temperature ofStep c) at a rate greater than 5 degrees C. per second, whereby theamorphous film is annealed at the intended temperature of Step c) for alarger crystal grain.

[0029] Step c) includes using a Rapid Thermal Annealing (RTA) process ata temperature of approximately 720 degrees C. and a time duration ofapproximately 2 minutes.

[0030] A thin-film transistor (TFT) comprising source/drain and channelregions of a single grain of crystallized film material is also providedThe amorphous film is doped with a transition metal at a firstconcentration, first density of nucleation sites, and a first distancebetween nucleation sites on an amorphous film. The amorphous film isannealed to form a first area of crystallized film, which is a singlegrain of crystal. A pattern is etched in the first area of crystallizedfilm to form the source/drain regions, whereby a transistor is formedhaving high electron mobility and low leakage current in the transistoractive areas.

BRIEF DESCRIPTION OF THE DRAWINGS

[0031] FIGS. 1-2 illustrate a conventional salicide process tocrystallize source/drain regions of a transistor (prior art).

[0032] FIGS. 3-4 illustrate a transistor being formed on a layer ofamorphous silicon, where silicidation metal is introduced outsidetransistor active regions (prior art).

[0033] FIGS. 5-7, 9-11, and 13-14 depict steps in the formation of acompleted thin-film transistor (TFT) comprising source/drain and channelregions of a single grain of crystallized first film material.

[0034]FIG. 8 is a graph detailing the relationship between transitionmetal deposition and crystal grain size.

[0035]FIGS. 12a through 12 c depict the delivery of the transition metaland the formation of the transition metal semiconductor compound duringannealment.

[0036]FIG. 15 is a flowchart illustrating steps in a method for forminglarge crystal grains.

[0037]FIG. 16 is a flowchart illustrating another aspect of a method offorming a crystallized film with large crystal grains.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0038] FIGS. 1-2 illustrate a conventional salicide process tocrystallize source/drain regions of a transistor (prior art). FIG. 1 isa plan view of a transistor 10 in fabrication having silicon source 12a, silicon drain 12 b, and silicon channel region 12 c. Silicon regions12 a, 12 b, and 12 c are surrounded by oxidized silicon 14, or a similarinsulating material. The source and drain regions 12 a and 12 b arecovered with a layer of transition metal 16. It is typical in thedeposition of transition metal layer 16 to cover surrounding areas 14,however, in the self-aligning silicide (salicide) process transitionmetal 16 only reacts with silicon. Therefore, metal 16 is not shownoverlying areas 14. Transition metal 16 is also not shown overlyingchannel region 12 c, since channel region 12 c is usually covered by agate oxide layer, and even a gate electrode at this stage of theprocess. Neither the gate oxide layer, nor gate electrode is shown forthe sake of clarity.

[0039]FIG. 2 illustrates transistor 10 of FIG. 1 following an annealingprocess. Transition metal 16 has moved along a lateral growth front outfrom silicon areas 12 a and 12 b. At the finish of the annealing processthe two growth fronts intersect in the center of the channel region,labeled 12 d. The silicon regions behind the growth front of transitionmetal 16 have been transformed with transition metal 16 intocrystallized silicon 18. That is, silicon areas 12 a, 12 b, and parts of12 c have been crystallized. Although the bulk of silicon areas 12 a and12 b may be crystallized silicon, devoid of transition metalsemiconductor compounds, such as silicide, the limited source ofamorphous silicon in area 12 c and the intersecting fronts may result inan area of silicide in channel region 12 d.

[0040] Typically, source drain areas 12 a and 12 b are amorphized inresponse to large doping implants in the formation of activesource/drain regions. When source/drain regions 12 a and 12 b areannealed again for implant activation, a danger exists that transitionmetal grains 16 in channel region 12 d could migrate back into theamorphous source/drain regions 12 a and 12 b. The presence of transitionmetal grains in source/drain regions 12 a and 12 b increases leakagecurrent as transition metal 16 tends to act as a short across thereverse bias junction. FIGS. 3-4 illustrate a transistor 110 beingformed on a layer of amorphous silicon 112, where silicidation metal 116is introduced outside transistor active regions (prior art). FIG. 3depicts source 112 a, drain 112 b, and channel 112 c to be formed fromamorphous silicon layer 112 after crystallization. During annealment, afront of transition metal 16, represented by arrows 117, grows acrosssilicon layer 12.

[0041]FIG. 4 illustrates transistor 110 after annealment. The lateralgrowth has continued through active areas 112 a, 112 b, and 112 c. Thatis, the front of unreacted transition metal 116, in the form of atransition metal semiconductor compound 117 has moved through siliconfilm 112. Behind the lateral growth front of transition metal 116 front,is a polycrystalline silicon 118. Actually, the entire sheet of silicon112 of FIG. 3 behind the growth front has been converted intopolycrystalline silicon 118, including active areas 112 a, 112 b, and112 c. The dotted lines running across polycrystalline film 118represent borders between areas of identical lattice alignment. Afterannealment, transition metal compounds in areas 116 and 117 are etchedaway. Transistor active areas 112 a, 112 b, and 112 c are free ofsilicide 117. However, a long annealing time was required because of thelong lateral crystallization length or growth front, represented byarrow 120. Further, silicide regions 116 and 117 cannot be used indevice fabrication, imposing restrictions upon device layout.

[0042] When metal is widely distributed into the semiconductor film, thedose of metal required for crystallization is generally lower than thedose required for selective introduction. However, metal-semiconductorcompounds tend to be randomly distributed in the semiconductor film,resulting in high leakage currents. Selective deposition allows controlover the areas in which the metal-semiconductor compounds reside. Butselective distribution required higher concentrations of metal. Highconcentrations of metal result in closely grouped nucleation sites and,ultimately, same crystal grains. The present invention permits selectiveplacement of transition metal and low transition metal concentrations.

[0043] FIGS. 5-7, 9-11, and 13-14 depict steps in the formation of atleast a single completed thin-film transistor (TFT) comprisingsource/drain and channel regions of a single grain of crystallized firstfilm material. FIG. 5 is a plan view of transistor 200. An amorphousfirst semiconductor film 202 is doped with a transition metal at a firstconcentration, first density of nucleation sites 204, and a firstdistance 206 between nucleation sites 204. First film material 202 isselected from the group consisting of silicon, germanium, siliconcarbide, and silicon-germanium compounds. The transition metal ofnucleation sites 204 is selected from the group consisting of Al, Ni,Ti, Co, and Pd.

[0044]FIG. 6 depicts of transistor 200 of FIG. 4 following annealing.Amorphous first film 202 is annealed to form a first area ofcrystallized first film 208. First area 208 (cross-hatched) is a singlegrain of crystal. In subsequent steps a pattern is etched into firstarea 208 of crystallized first film to form the source/drain regions 209(double cross-hatched), whereby a transistor is formed having highelectron mobility and low leakage current in the transistor activeareas. Areas 210 and 212 are single crystal grains for the fabricationof neighboring transistors. In some aspects of the invention, thesubsequently formed transistors overlie neighboring areas ofcrystallized film, such as areas 208, 210, and 212. In thosecircumstances a transistor is formed from multiple crystal grains.

[0045]FIG. 7 is a partial cross-sectional view of transistor 200 of FIG.5. Amorphous first film 202 has a thickness 213 in the range from 200 to10,000 Å. Amorphous first film 202 is doped with transition metal 204through a transition metal window 214. That is, nucleation sites 204 areformed within a rectangular window 214 overlying the subsequently formedfirst area 210 (also areas 210 and 212) of crystallized film. In FIG. 6,where at least a second (and third) TFT is to be formed adjoining thefirst TFT 209, such as on crystallized areas 210, and 212, transitionmetal 214 is doped within a rectangular window overlying crystallizedfirst film areas 208, 210, and 212 having a width 216 in the range from20 to 50 microns, and a length 218 of 50 microns, or greater. When oneTFT is to be fabricated, transition metal is doped within a rectangularwindow overlying first crystallized area 208 having a width 216 in therange from 20 to 50 microns and a length 218 a in the range from 60 to150 microns. The ratio of transition metal window 214 area, of length218 a and width 216 to area 208 of crystallized film is in the rangefrom 1:1 to 1:3. That is, first area 208 is 1 to 3 times larger thanwindow 214 area. First area 208 of crystallized first film is in therange from 20 to 8,000 square microns (μ²). FIG. 6 depicts approximately1:1 ratio.

[0046] Returning to FIG. 7, an insulator or photoresist mask 220 is usedto define window 214. TFT 200 further comprising a glass substrate 222.In some aspects of the invention, a barrier layer 224 overlies glasssubstrate 222. Then, first area 208 of crystallized first film is formedoverlying barrier level 224.

[0047] The heart of the invention is the relationship between annealingtemperature, transition metal concentration, transition metal density,and the spacing between nucleation sites. In the prior art, aconcentration of 2×10¹⁹ atoms per cubed centimeter typically lead to anincrease in the transition metal nucleation site density above 1×10⁷ persquare centimeter. At these higher densities, the spacing betweennucleation sites decreases, so that smaller crystal grain are formed.However, when the concentration of transition metal falls too far below2×10¹⁹ atoms per cubed centimeter, there is insufficient metal tosupport the lateral growth of transition metal semiconductor compounds,such as di-silicide, during annealment.

[0048] Transition metal 204 doping is selected from the group consistingof ion implantation and CVD deposition methods. The first concentrationof transition metal is less than 2×10¹⁹ atoms per cubed centimeter, andthe first density of transition metal nucleus sites are less than 1×10⁷per square centimeters. Only three nucleation sites are shown in FIGS.5-7 for the purpose of clarity. First distance 206 between transitionmetal nucleus sites 204 is no less than 2 microns.

[0049]FIG. 8 is a graph detailing the relationship between transitionmetal deposition and crystal grain size. To alleviate theabove-mentioned transition metal concentration problem, a continuoustransition metal delivery system was developed. That is, transitionmetal implanting occurs, at least partially, simultaneously with theannealing of said first film, whereby said transition metal iscontinually introduced during the annealing process to support thelateral growth of crystallization. FIG. 8 shows that at a nucleationdensity of 1×10⁷/cm², the concentration of Ni atoms is approximately2×10¹⁹ atoms/cm³, and the nearest neighbor distance (N.N.D.) is 2microns.

[0050] Annealing is performed with an RTA process at a temperature inthe range from 600 to 800 degrees C., for a time duration in the rangefrom 1 second to 15 minutes. In one aspect of the invention, annealingis performed with an RTA process at a temperature in the range from 700to 750 degrees C., for a time duration in the range from 1 to 5 minutes.In one preferred embodiment, the annealing is performed with an RTAprocess at a temperature at approximately 720 degrees C. and a timeduration of approximately 2 minutes. In one aspect of the invention, thetemperature is ramped-up to the annealing temperature at a rate greaterthan 5 degrees C. per second, whereby the first film is annealed at theintended temperature for larger crystal grains.

[0051]FIG. 9 is a partial cross-sectional view of a TFT 300 fabricatedin accordance with the present invention. TFT 300 is comprised of atransparent substrate 222, and overlying barrier level 224. An amorphousfilm 202 overlies barrier level 224. An insulator film 302 having afirst thickness 304 is deposited over amorphous first film 202.Insulator film 302 has a first thickness 304 in the range from 10 to 100Å. Insulator material 302 is selected from the group consisting ofsilicon dioxide and silicon nitride.

[0052] Transition metal 306 is deposited overlying insulator film 302.Transition metal 306 is deposited with a thickness 307 in the range from10 to 1000 Å. During annealing, transition metal 306 diffuses throughinsulator film 302 into said amorphous first film 202. In this manner,the formation of transition metal nucleus sites 204 (see FIGS. 5-7) iscontrolled. Transition metal doping occurs, at least partially,simultaneously with the annealing of first film 202. Transition metal306 is continually introduced during the annealing process to supportthe lateral growth of crystallization.

[0053]FIG. 10 depicts TFT 300 of FIG. 9 following an etching step.Transition metal 306 overlying insulator film 302 is selectively etchedbefore annealing to form a window 308 of transition metal 306. FIG. 10shows only the width 310 of window 308. In this manner, the size offirst area 208 of crystallized first film is influenced (see FIG. 6).

[0054] Alternately, FIG. 11a depicts a transparent substrate 222, andoverlying barrier level 224. An amorphous film 202 overlies barrierlevel 224. An insulator film 302 has an initial thickness 304 a, of 500Å, or greater, is deposited over amorphous first film 202. FIG. 11bdepicts insulator film 302 following selective etching to form an areahaving a first thickness 304, less than initial thickness 304 a.Transition metal 306 is deposited over first thickness 304 to formtransition metal window 308, whereby the size of first area 208 ofcrystallized first film is influenced (see FIG. 6).

[0055]FIGS. 12a through 12 c depict the delivery of transition metal 304and the formation of transition metal semiconductor compound 316 duringannealment. FIG. 12a shows transistor 300 with insulator film 302overlying amorphous film 202, such as Si. Transition metal 306, such asNi, overlies Si 202. Transition metal window 308 is formed by the stepsillustrated in FIGS. 9-10, and by the steps depicted in FIGS. 11a and 11b.

[0056] As shown in FIG. 12b, during annealment, Ni atoms diffuse throughinsulator film 302 uniformly. Thickness 304 of insulator film 302 andthickness 307 of Ni film 306 are varied to control the concentration ofNi.

[0057]FIG. 12c depicts the concentration of Ni atoms 306 in the laterstages of annealment. A nucleation site 204 is formed in the center ofwindow 308, with relatively low concentrations of Ni atoms 306 is theremaining area of window 308.

[0058] Returning briefly to FIG. 6, transition metal semiconductorcompounds 316 surrounding first area 208 of crystallized first film areremoved when source/drain regions 209 are defined after annealing,whereby crystallized film is cleaned of materials which promote highleakage currents.

[0059]FIG. 13 depicts further fabrication steps of transistor 300 ofFIG. 10 after annealing and transition metal semiconductor compound 316removal. An oxide layer 320 overlies the channel region 322. A gateelectrode 324 overlies oxide layer 322. In some aspects of theinvention, phosphorous 326 is implanted into source 328 and drain 330regions. Alternately, boron 326 is implanted. Annealing is performed toactivate implanted species 326.

[0060]FIG. 14 depicts TFT 300 of FIG. 13 following the removal of oxidelayer 320. A gate oxide layer 332 remains, gate electrode 324 overliesgate oxide layer 332. A dielectric interlevel 334 is deposited overtransistor 300. Contact holes 336 are defined through dielectricinterlevel 334 and metal 338 is deposited in contact holes 336 so thatan electrical interface is made to source/drain regions 328/330. In thismanner, a top gate TFT is fabricated. Alternately, but not shown, abottom gate TFT is fabricated by depositing gate electrode 324 and gateoxide layer 332 before deposited first film 202, as is well known in theart.

[0061]FIG. 15 is a flowchart illustrating steps in a method for forminglarge crystal grains. Step 400 provides an amorphous film. Step 402deposits a layer of the amorphous first film. Step 402 includes anamorphous first film selected from the group consisting of silicon,germanium, silicon carbide, and silicon-germanium compounds. Step 402includes an amorphous first film having a thickness in the range from200 to 10,000 Å. Step 404 dopes the amorphous first film with a firstconcentration of transition metal, to form a first density of transitionmetal nucleus sites, with the nucleation sites being separated by afirst distance. In this manner, a low density of nucleation sites isformed. Step 406 anneals to form a first area of a single grain ofcrystallized first film. Step 408 is a product, a crystallized filmprepared for the fabrication of a single crystal transistor.

[0062] A further step, follows Step 406. Step 406 a removes transitionmetal semiconductor compound surrounding the first area of crystallizedfirst film, whereby the film is cleaned of materials which promote highleakage currents.

[0063] In some aspects of the invention, Step 404 includes using an ionimplantation method to dope amorphous first film with transition metalwithin a rectangular window. It is convenient to describe the transitionmetal window as a rectangular window that varies from approximately asquare, or circular shape to an elongated strip. Alternately, the windowmay be other shapes with the same approximate area as described below.When a single first crystallized area is to be formed in Step 406, Step404 includes doping within a rectangular transition metal window havinga width in the range from 20 to 50 microns and a length in the rangefrom 60 to 150 microns. The smaller width measurement correspond tosmaller length measurements. The ratio of the area of the transitionmetal window of Step 402 b to the first area of crystallized film ofStep 406 is in the range from 1:1 to 1:3.

[0064] When at least a second area of single grain crystallized film isformed in Step 406, such as when series of crystallized areas is formedalong an elongated strip of first film to form a series of transistors,Step 404 includes doping within a transition metal window having a widthin the range from 20 to 50 microns and a length of 50 microns, orgreater.

[0065] In other aspects of the invention, Step 404 is performed, atleast partially, simultaneously with Step 406, whereby transition metalis continually introduced during the annealing process to support thelateral growth of crystallization. Then, the method includes furthersteps following Step 402. Step 402 a deposits an insulator film having afirst thickness overlying the amorphous first film. Step 402 a includesan insulator layer first thickness in the range from 10 to 100 Å. Step402 a includes an insulator material selected from the group consistingof silicon dioxide and silicon nitride. Step 402 b deposits thetransition metal overlying the insulator film first thickness. Step 402b includes depositing transition metal having a thickness in the rangefrom 10 to 1000 Å. The transition metal selected from the groupconsisting of Al, Ni, Ti, Co, and Pd. Then, Step 406 includes thediffusion of transition metal through the insulator film first thicknessinto the amorphous first film, whereby the density of transition metalnucleuses is controlled.

[0066] In some aspects of the invention, Step 402 b selectively etchesthe transition metal deposited in Step 402 b to form a window oftransition metal, whereby the size of the first area of crystallizedfilm is influenced. In other aspects of the invention, Step 402 aincludes depositing the insulator film with an initial thickness of 500Å, or greater. The insulator film is selectively etched to form an areahaving a first thickness, less than the initial thickness. Then, Step402 b includes forming a window of transition metal over the insulatorfilm first thickness, whereby the size of the first area of crystallizedfilm is influenced.

[0067] Step 406 includes the first area of crystallized first film beingin the range from 20 to 8,000 square microns (μ²) Typically, Step 402 bincludes the transition metal window being a rectangle having a width inthe range from 20 to 50 microns and a length in the range from 60 to 150microns, as explained above with the ion implantation process. Likewise,when Step 406 includes forming at least a second area of crystallizedfirst film, Step 402 b includes the transition metal window being arectangle having a width in the range from 20 to 50 microns and a lengthof 50 microns, or greater.

[0068] In some aspects of the invention, Step 404 includes a firstconcentration of transition metal no more than 2×10¹⁹ atoms per cubedcentimeter, and the first density of transition metal nucleus sites nomore than 1×10⁷ square centimeters. Step 404 includes a first distancebetween transition metal nucleus sites of no less than 2 microns.

[0069] In some aspects of the invention, further steps, precede Step406. Step 404 a ramps-up the temperature to the annealing temperature ofStep 406 at a rate greater than 5 degrees C. per second, whereby thefirst film is annealed at the intended temperature of Step 406 for alarger crystal grain.

[0070] Step 406 includes using a Rapid Thermal Annealing (RTA) processat a temperature in the range from 600 to 800 degrees C., and a timeduration in the range from 1 second to 15 minutes. In one aspect of theinvention, Step 406 includes using a Rapid Thermal Annealing (RTA)process at a temperature in the range from 700 to 750 degrees C., and atime duration in the range from 1 to 5 minutes. In another aspect of theinvention, Step 406 includes using a Rapid Thermal Annealing (RTA)process at a temperature of approximately 720 degrees C. and a timeduration of approximately 2 minutes.

[0071] When a TFT is be fabricated, Step 400 provides a glass substrateand a barrier layer overlying the glass substrate. Then, Step 402includes depositing the first film overlying the barrier layer and glasssubstrate. Further steps (not shown), are involved. When a top gatetransistor is to be performed, additional steps follow Step 406. Step406 b forms transistor source, drain, and channel regions within thefirst area of crystallized film, whereby the source, drain, and channelregions are formed from a single crystal grain, without the presence oftransition metal semiconductor compounds. Step 406 c forms a gate oxidelayer. Step 406 d forms a gate electrode. Step 406 e implants dopingspecies. Step 406 f anneals to activate the implanted species, whereby atop gate TFTs is formed. When a bottom gate TFT is formed, Steps 406 cand 406 d precede Step 402, as is well known in the art.

[0072]FIG. 16 is a flowchart illustrating another aspect of a method offorming a crystallized film with large crystal grains. Step 500 providesa semiconductor film and a transition metal. Step 502 heats thesemiconductor film to a temperature in the range from 700 to 750 degreesC. Step 504 heats the semiconductor film for a duration in the rangefrom 1 to 5 minutes. Step 506 supplies a transition metal concentrationof no more than 2×10¹⁹ atoms/cm³. Step 508 maintains a transition metalnucleation site density of no more than 1×10⁷/cm². Step 510 maintains adistance between transition metal nucleation sites of less than 2microns. Step 512 forms large grains of crystallized semiconductor filmcorresponding to the distance between transition metal nucleation sites.

[0073] A TFT fabricated from a single crystal grain, and fabricationmethod has been provided. A large crystal grain is made by precisecontrol of annealment, transition metal concentration, the density oftransition metal nucleation sites, and the distance between nucleationsites. In one aspect of the invention, a diffusion layer permits thecontinual delivery of transition metal at a rate that both supports thelateral growth of di-silicide, and large distances between nucleationsites. Other variations and embodiments of the invention will occur tothose skilled in the art.

What is claimed is:
 1. A method for crystallizing an amorphous film intolarge grains comprising the steps of: a) depositing a layer of theamorphous first film; b) doping the amorphous first film with a firstconcentration of transition metal, to form a first density of transitionmetal nucleus sites, with the nucleation sites being separated by afirst distance, whereby a low density of nucleation sites is formed; andc) annealing to form a first area of a single grain of crystallizedfirst film, whereby a crystallized film is prepared for the fabricationof a single crystal transistor.
 2. A method as in claim 1 including afurther step, following Step c), of: d) removing transition metalsemiconductor compound surrounding the first area of crystallized firstfilm, whereby the film is cleaned of materials which promote highleakage currents.
 3. A method as in claim 1 in which Step b) includesusing an ion implantation method to dope amorphous first film withtransition metal within a rectangular window having a width in the rangefrom 20 to 50 microns.
 4. A method as in claim 1 in which Step b)includes using an ion implantation method to dope amorphous first filmwith transition metal within a rectangular window having a length in therange from 60 to 150 microns.
 5. A method as in claim 3 in which Step b)includes using an ion implantation method to dope amorphous first filmwith transition metal within a rectangular window having a width in therange from 20 to 50 microns and a length of 50 microns, or greater, andin which Step c) includes forming at least a second area of a singlegrain crystallized first film.
 6. A method as in claim 1 in which Stepb) is performed, at least partially, simultaneously with Step c),whereby transition metal is continually introduced during the annealingprocess to support the lateral growth of crystallization.
 7. A method asin claim 6 including further steps, following Step a), of: a₁)depositing an insulator film having a first thickness overlying theamorphous first film; a₂) depositing the transition metal overlying theinsulator film first thickness to form a window of transition metal; andin which Step c) includes the diffusion of transition metal through theinsulator film first thickness into the amorphous first film, wherebythe density of transition metal nucleuses is controlled.
 8. A method asin claim 7 in which Step a₂) includes selectively etching the transitionmetal deposited in Step a₂) to form a window of transition metal,whereby the size of the first area of crystallized film is influenced.9. A method as in claim 7 in which Step a₁) includes depositing theinsulator film with an initial thickness, in which the insulator film isselectively etched to form an area having a first thickness, less thanthe initial thickness, and in which Step a₂) includes forming a windowof transition metal over the insulator film first thickness, whereby thesize of the first area of crystallized film is influenced.
 10. A methodas in claim 7 in which the ratio of the area of the transition metalwindow of Step a₂), to the first area of crystallized film is in therange from 1:1 to 1:3.
 11. A method as in claim 10 in which Step c)includes the first area of crystallized first film being in the rangefrom 20 to 8,000 square microns (μ²).
 12. A method as in claim 7 inwhich Step a₂) includes the transition metal window being a rectanglehaving a width in the range from 20 to 50 microns.
 13. A method as inclaim 7 in which Step a₂) includes the transition metal window being arectangle having a length in the range from 60 to 150 microns.
 14. Amethod as in claim 7 in which Step a₂) includes the transition metalwindow being a rectangle having a width in the range from 20 to 50microns and a length of 50 microns, or greater, and in which Step c)includes forming at least a second area of crystallized first film. 15.A method as in claim 9 in which Step a₁) includes depositing aninsulator layer having an initial thickness of 500 Å, or greater.
 16. Amethod as in claim 7 in which Step a₁) includes an insulator firstthickness in the range from 10 to 100 Å.
 17. A method as in claim 7 inwhich Step a₁) includes an insulator material selected from the groupconsisting of silicon dioxide and silicon nitride.
 18. A method as inclaim 7 in which Step a₂) includes depositing transition metal having athickness in the range from 10 to 1000 Å.
 19. A method as in claim 1 inwhich Step b) includes the first concentration of transition metal beingno more than 2×10¹⁹ atoms per cubed centimeter.
 20. A method as in claim1 in which Step b) includes the first density of transition metalnucleus sites being no more than 1×10⁷ square centimeters.
 21. A methodas in claim 1 in which Step b) includes a first distance betweentransition metal nucleus sites of no less than 2 microns.
 22. A methodas in claim 1 in which Step b) includes depositing a transition metalselected from the group consisting of Al, Ni, Ti, Co, and Pd.
 23. Amethod as in claim 1 including further steps, preceding Step c), of: b₁)ramping the temperature up to the annealing temperature of Step c) at arate greater than 5 degrees C. per second, whereby the first film isannealed at the intended temperature of Step c) for a larger crystalgrain.
 24. A method as in claim 1 in which Step c) includes using aRapid Thermal Annealing (RTA) process at a temperature in the range from600 to 800 degrees C., and a time duration in the range from 1 second to15 minutes.
 25. A method as in claim 24 in which Step c) includes usinga Rapid Thermal Annealing (RTA) process at a temperature in the rangefrom 700 to 750 degrees C., and a time duration in the range from 1 to 5minutes.
 26. A method as in claim 25 in which Step c) includes using aRapid Thermal Annealing (RTA) process at a temperature of approximately720 degrees C. and a time duration of approximately 2 minutes.
 27. Amethod as in claim 1 wherein a glass substrate is provided, and in whichStep a) includes depositing the first film overlying the glasssubstrate.
 28. A method as in claim 1 including the further steps of: e)forming transistor source, drain, and channel regions within the firstarea of crystallized film, whereby the source, drain, and channelregions are formed from a single crystal grain, without the presence oftransition metal semiconductor compounds; f) forming a gate oxide layer;g) forming a gate electrode; h) implanting doping species; and i)annealing to activate the implanted species, whereby both top gate andbottom gate TFTs are formed.
 29. A method as in claim 1 in which Step a)includes an amorphous first film selected from the group consisting ofsilicon, germanium, silicon carbide, and silicon-germanium compounds.30. A method as in claim 1 in which Step a) includes an amorphous firstfilm having a thickness in the range from 200 to 10,000 Å.
 31. A methodof annealing a semiconductor film with a transition metal to form acrystallized film with large crystal grains, the method comprising thesteps of: a) heating the semiconductor film to a temperature in therange from 700 to 750 degrees C.; b) heating the semiconductor film fora duration in the range from 1 to 5 minutes; c) supplying a transitionmetal concentration of no more than 2×10¹⁹ atoms/cm³; d) maintaining atransition metal nucleation site density of no more than 1×10⁷/cm²; e)maintaining a distance between transition metal nucleation sites of noless than 2 microns; and f) forming large grains of crystallizedsemiconductor film corresponding to the distance between transitionmetal nucleation sites.
 32. A first thin-film transistor (TFT)comprising source/drain and channel regions of a single grain ofcrystallized first film material formed from doping an amorphous firstfilm with a transition metal through a transition metal window at afirst concentration, first density of nucleation sites, and a firstdistance between nucleation sites, annealing said amorphous first filmto form a first area of crystallized first film which is a single grainof crystal, and etching a pattern in said first area of crystallizedfirst film to form the source/drain regions, whereby a transistor isformed having high electron mobility and low leakage current in thetransistor active areas.
 33. A TFT as in claim 32 further comprising: agate electrode; a gate oxide layer overlying said gate electrode; and inwhich said gate electrode and gate oxide layer are deposited before saidfirst film, whereby a bottom gate TFT is fabricated.
 34. A TFT as inclaim 32 further comprising: a gate oxide layer overlying said channelregion; and a gate electrode overlying said gate oxide layer, whereby atop gate TFT is fabricated.
 35. A TFT as in claim 32 in which said firstfilm material is selected from the group consisting of silicon,germanium, silicon carbide, and silicon-germanium compounds.
 36. A TFTas in claim 32 in which the transition metal is selected from the groupconsisting of Al, Ni, Ti, Co, and Pd.
 37. A TFT as in claim 32 in whichthe temperature is ramped-up to the annealing temperature at a rategreater than 5 degrees C. per second, whereby the first film is annealedat the intended temperature for larger crystal grains.
 38. A TFT as inclaim 32 in which the annealing is performed with an RTA process at atemperature in the range from 600 to 800 degrees C., for a time durationin the range from 1 second to 15 minutes.
 39. A TFT as in claim 38 inwhich the annealing is performed with an RTA process at a temperature inthe range from 700 to 750 degrees C., for a time duration in the rangefrom 1 to 5 minutes.
 40. A TFT as in claim 39 in which the annealing isperformed with an RTA process at a temperature at approximately 720degrees C. and a time duration of approximately 2 minutes.
 41. A TFT asin claim 32 in which transition metal semiconductor compound surroundingsaid first area of crystallized first film is removed when saidsource/drain regions are defined, whereby said crystallized film iscleaned of materials which promote high leakage currents.
 42. A TFT asin claim 32 in which said transition metal is doped within a rectangularwindow overlying said first area of crystallized film, having a width inthe range from 20 to 50 microns.
 43. A TFT as in claim 32 in which saidtransition metal is doped within a rectangular window overlying saidfirst area of crystallized film, having a length in the range from 60 to150 microns.
 44. A TFT as in claim 32 wherein at least a second TFT isformed adjoining the first TFT, in which at least a second area ofcrystallized first film is formed adjoining said first area ofcrystallized first film, and in which said transition metal is dopedwithin a rectangular window overlying said first and second areas ofcrystallized film having a width in the range from 20 to 50 microns anda length of 50 microns, or greater.
 45. A TFT as in claim 32 in whichsaid amorphous first film is doped with said transition metal to saidfirst concentration of transition metal less than 2×10¹⁹ atoms per cubedcentimeter.
 46. A TFT as in claim 32 in which said amorphous first filmis doped with said transition metal to said first density of transitionmetal nucleus sites is less than 1×10⁷ square centimeters.
 47. A TFT asin claim 32 in which the first distance between said transition metalnucleus sites is no less than 2 microns.
 48. A TFT as in claim 32 inwhich the ratio of said transition metal window area to said first areaof crystallized film is in the range from 1:1 to 1:3.
 49. A TFT as inclaim 32 in which said first area of crystallized first film is in therange from 20 to 8,000 square microns (μ²).
 50. A TFT as in claim 32 inwhich transition metal doping is selected from the group consisting ofion implantation and CVD deposition.
 51. A TFT as in claim 32 in whichsaid transition metal doping occurs, at least partially, simultaneouslywith the annealing of said first film, whereby said transition metal iscontinually introduced during the annealing process to support thelateral growth of crystallization.
 52. A TFT as in claim 51 in which aninsulator film having a first thickness is deposited over said amorphousfirst film, with said transition metal being deposited overlying saidinsulator film, and in which said transition metal diffuses through saidinsulator film into said amorphous first film first thickness duringannealing, whereby the formation of said transition metal nucleuses iscontrolled.
 53. A TFT as in claim 52 in which said transition metaloverlying said insulator film is selectively etched before annealing toform said transition metal window, whereby the size of said first areaof crystallized first film is influenced.
 54. A TFT as in claim 52 inwhich said insulator film is deposited with an initial thickness andselectively etched to form an area having a first thickness, less thanthe initial thickness, and in which said transition metal is depositedover said first thickness of insulator film to form said transitionmetal window, whereby the size of said first area of crystallized filmis influenced.
 55. A TFT as in claim 54 in which said initial thicknessis 500 Å, or greater.
 56. A TFT as in claim 52 in which said insulatorfilm has a first thickness in the range from 10 to 100 Å.
 57. A TFT asin claim 52 in which said insulator material is selected from the groupconsisting of silicon dioxide and silicon nitride.
 58. A TFT as in claim52 in which said transition metal is deposited with a thickness in therange from 10 to 1000 Å.
 59. A TFT as in claim 32 further comprising aglass substrate, and in which said crystallized first film is formedoverlying said glass substrate.
 60. A TFT as in claim 32 in which saidamorphous first film has a thickness in the range from 200 to 10,000 Å.